The ISC High Performance conference will bring together over 3,500 researchers and commercial users, … Read more about Maestro at the ISC 2019
Maestro will build a data and memory-aware middleware framework that addresses the ubiquitous problems of data movement in complex memory hierarchies that exist at multiple levels of the HPC software stack.
Moving data through memory has not always been a performance bottleneck. The software stack that HPC relies upon was built during the decades where the cost of performing floating point operations (FLOPS) was paramount. This has resulted in a software stack and set of programming models that are optimised for floating point operations but lacking in basic data handling functionality. We characterise the set of technical issues as ‘missing data-awareness’.
Software rightfully insulates users from hardware details, particularly as we move up the software stack. But HPC applications, programming environments and system software cannot make key data movement decisions without some understanding of the hardware, particularly of the increasingly complex memory hierarchy. With the exception of runtimes, which treat memory in a domain-specific manner, software typically makes hardware-neutral decisions which can often result in poor performance We characterise this issue as ‘missing memory-awareness’.
A Coruña, Spain, 25th October 2018. Appentra, the CEA, Cray, CSCS operated by ETH Zurich, ECMWF, … Read more about Maestro Consortium addresses the ubiquitous problems of data movement in data-intensive applications and workflows
Presentation: MAESTRO: Middleware for Memory and Data-Awareness in Workflows Information:
Presentation: MAESTRO: Middleware for Memory and Data-Awareness in Workflows
Information: Presentation by François Tessier from CSCS.
More info here.
9 (Monday) 0:00 - 11 (Wednesday) 0:00