The Jülich Supercomputing Centre (JSC) has more than 30 years of expertise in providing supercomputer services to national and international user communities. It undertakes research and development in HPC architectures, performance analysis, HPC applications, Grid computing and networking.
JSC operates several supercomputers and high-end storage systems and makes them available for research and engineering. Most of the resources are allocated to research and engineering projects at local, national and European level based on excellence, e.g. through PRACE [http://www.prace-ri.eu/].
To facilitate advanced user support, JSC has built-up a number of Simulation Laboratories to further enhance its competence in key computational sciences areas including computational biology, molecular systems, plasma physics, climate modelling and neuroscience. The institute furthermore engages strongly with different research communities, e.g. with the brain research community through the Human Brain Project.
Another focus of research at JSC is the development of HPC architectures and technologies. By means of co-design and industrial collaborations, JSC contributes to the development and creation of new solutions, which are needed to reach exascale performance levels in the future.
Role in MAESTRO
JSC as a leading supercomputing centre in Europe has a strong interest in new technologies being developed that enables scientific computing but also emerging data science applications being able to leverage the performance of future exascale architectures. JSC is responsible for driving co-design through an application from the area of earth system modelling and aims to also contribute to the work on applications from materials sciences research and computational fluid dynamics.
Furthermore, JSC will lead the efforts related to the high-level middleware, which will result in middleware components concerned with data access and dataflow as well as data-aware execution and orchestration.
CEA as a whole is a major player throughout the value chain of HPC from R&D in the development of silicon technology, architecture of processors, system integration, software environments and tools through to use of numerical simulation in many different areas related to the missions of CEA. It has more than 16000 staff members in the development of low carbon energies, technologies for health, information technology, defence and global security, and underlying fundamental research for all these objectives. CEA also owns and operates two world-class computing infrastructures (TERA and TGCC), and deploys related HPC services, for the benefit of national and European research, defense, and industry, Industrial access to HPC has been deployed for 10 years at CEA CCRT, through an original partnership business model and a dedicated supercomputer of nearly 0.5 petaflop/s. CEA DIF DSSI is the division in charge of HPC at CEA, located in the Paris Region. DSSI operates the aforementioned computing centres and leads R&D in hardware and software technologies for HPC systems. (See http://www-hpc.cea.fr)
Role in Maestro CEA will extend and develop new features in existing open source projects MPC, PaDaWAn and SelFIe to support or be used by Maestro middleware. CEA will adapt a production workflow to exploit Maestro-enabled data-driven optimisation. By adapting these tools to use Maestro the CEA software environment can be readied for Exascale. The telemetry developments will be used to monitor production on CEA computing centers. CEA will bring it’s experstise in running world class computing centers based and in the design and devlopement of opensource tools for high performance data/computing centers.
Appentra is a technology-based company spin-off of the University of A Coruña (UDC) founded in July 2012, with worldwide exclusive rights to develop, commercialise, and support products and services based on the Parallware technology, as specified in the technology transfer agreement between Appentra and UDC. The company headquarters are in the Research Center on Information and Communication Technologies (CITIC) of the University of A Coruña (Spain). The Parallware Technology is the result of over 10 years of world-class, international research and development in the field of advanced compiler technologies for programming environments that use automatic parallelisation of sequential codes to manage the complexity that HPC developers face in modern HPC facilities. The research is headed by Manuel Arenaz (PhD) who is promoter, founder and current CEO/CTO of Appentra. The initial technological development to move from experimental R&D prototype up to TRL 6 (Minimum Viable Product – MVP) was financed through the prestigious CDTI NEOTEC funds of the Government of Spain, restricted to innovative and disruptive technology companies with their own R&D strategy, a good business plan, and broad scientific technical mastery of the field. The company has already raised high interest from world-class supercomputing centres such as OLCF, JSC, and BSC, with key staff in the centres publicly supporting the promotion of new Parallware-powered software tools within the HPC community.
Role in Maestro Appentra Solutions will enhance their Parallelware software for data awareness to support the Maestro middleware.
ETH Zurich is represented in MAESTRO by the Swiss National Supercomputing Centre (CSCS). Founded in 1991, CSCS develops and provides the key supercomputing capabilities required to solve challenging problems in science and society. The centre enables world-class research with a scientific user lab that is available to domestic and international researchers. CSCS’s resources are open to academia and are available as well to users from industry and the business sector.
Role in Maestro Efficient data movements are of paramount importance for current and future HPC systems. New complex workflows combining traditional HPC applications together with High-Performance Data Analysis techniques require to read and write an increasing amount of data. In the same time, to enable fast access to data and reduce data movements, vendors have deployed new tiers of memory and storage at various levels of the HPC architecture. In this context, MAESTRO proposes to develop a middleware in charge of orchestrating data movement on large-scale platforms to accommodate complex scientific workflows. To achieve such solution, hardware and software resources have to be described to MAESTRO and then exposed to the applications and workflows. It is the assignment of ETH Zurich inside this project to create a dynamic resource provisioning mechanism ensuring data isolation and coherency for all the applications and workflows interacting with MAESTRO. CSCS provides the MAESTRO consortium with expertise in data management at scale. One of the roles of CSCS is to develop a dynamic resource provisioning system as a crucial component of the MAESTRO middleware.
ECMWF is both a research institute and a 24/7 operational service, producing and disseminating medium- and extended-range weather forecasts to its member states, worldwide commercial customers and international organisations (e.g. the UN/WFP, IAEA, etc). To that effect, ECMWF operates a supercomputer facility that is one of the largest of its type, and an associated perpetual archive of meteorological data. Furthermore, ECMWF pursues scientific and technical collaborations with satellite agencies, the European meteorological community and the world climate and weather prediction communities, as well as providing services for the European Commission. The principal objectives of ECMWF are (1) the development of numerical methods for medium-range weather forecasting; (2) the preparation, on a regular basis, of medium-range weather forecasts for distribution to the meteorological services; (3) scientific and technical research directed at the improvement of these forecasts; (4) the collection and storage of appropriate meteorological data.
Role in Maestro ECMWF leads WP2, bringing its long experience in developing numerical weather prediction applications and running time-critical HPC operational services to the analysis of application and workflow requirements within Maestro, and the co-design of the Maestro middleware. ECMWF also contributes significantly to the validation and demonstration of the Maestro middleware through use of its forecasting application developments to its data and I/O software stack.
HPE participates in MAESTRO through its HPC/AI EMEA Research Lab, formerly CRAY EMEA Research Lab, located in Basel, Bristol and Grenoble. The HPE HPC/AI EMEA Research Lab is HPE’s department for future technology research in the HPE HPC/AI European division. The HPE HPC/AI EMEA Research Lab is currently lead by Master Research Engineer Utz-Uwe Haus, and focuses on deep technical engagements with the European HPC and academic communities. It has current research projects in data-centric optimization, unified data models including memory reuse optimization using polyhedral compilation techniques, workflow management and optimization, adaptive transport methods and tasking frameworks for resilience. The Advanced Collaboration Centres at KAUST, EPCC and GW4 are also operated by the HPC/AI EMEA Research Lab.
Role in Maestro
The HPE HPC/AI EMEA Research Lab is providing overall technical coordination of the Maestro project. In addition, it is responsible for the development of the core Maestro Middleware, the design of the underlying abstractions, the co-design of application interfaces to Maestro and the development of a data-aware runtime demonstrator.